The present disclosure relates generally to electronic memory technology, and more specifically to mismatch and noise insensitive spin torque transfer magnetic random access memory (STT-MRAM).
STT MRAM is an attractive emerging memory technology, offering non-volatility, high performance and high endurance. A typical STT MRAM memory cell includes a magnetic tunnel junction (MTJ) in series with a field effect transistor (FET), which is gated by a word line (WL). A bitline (BL) and a source line (SL) run parallel to each other and perpendicular to the WL. The BL is connected to the MTJ, and the SL is connected to the FET. One memory cell along the BL is selected by turning on its WL. When a relatively large voltage (e.g., 500 mV) is forced across the cell from BL to SL, the selected cell's MTJ is written into a particular state, which is determined by the polarity of this voltage (BL high vs. SL high).
When the cell is in a logic zero (0) or parallel state, its MTJ resistance is lower than when the cell is in a logic one (1) or anti-parallel state. Typical MTJ resistance values would include R0=10 KΩ and R1=20 KΩ. A selected cell is read by sensing the resistance from BL to SL. The “sense” or “read” voltage must be much lower than the write voltage in order to clearly distinguish write and read operations, and to avoid inadvertently disturbing the cell during a read operation. Thus, sensing methodologies must be capable of accurately sensing very low read voltage (e.g., less than 50 mV). The state-dependent change in resistance is characterized by the parameter MR or magnetoresistance, which is defined as MR=(R1−R0)/R0. 100% is a typical nominal value for MR, although higher values have been reported.